High Speed Bipolar Latch Design for Large Scale Integration

High Speed Bipolar Latch Design for Large Scale Integration

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This dissertation presents the analysis and design of high-speed bipolar D-Flip-Flops. A conventional current mode logic (CML) static frequency divider (SFD) design in a high-speed InP process is shown. The SFD was the fastest CML divider at the time of publication. A new flip-flop topology more suitable for large scale circuits is presented and compared with a standard CML flip-flop. The new flip-flop incorporates a translinear current amplifier (also known as a qGilbert Gain Cellq) internally to reduce the load presented by the flip-flop to the clock network. The combined flip-flop and clock network uses less current while performing at a similar rate of speed compared with the standard CML flip-flop. This is demonstrated in a SiGe process and results show an improvement in the power-delay product of approximately 14%, running at top speed. The new flip-flop is simulated in a Pseudo Random Bit Stream (PRBS) generator and compares favorably to a PRBS generator using the conventional CML flip-flop.Layout. of. LFSR. The primary concern in laying out the circuit was to create a compact design, and to ensure that the ... 6.6 shows a more physical block diagram. ... reaches the critical XOR gate, increasing the setup time for the XOR latch.

Title:High Speed Bipolar Latch Design for Large Scale Integration
Publisher:ProQuest - 2007

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